There is no space in the beginning of this line, In the example below, the string variable called addr gets the value "Earth " because of preservation of spaces in strings. However blanks(spaces) and tabs (from TAB key) are not ignored in strings. Reg name = "Hello!" // The 2 spaces in the beginning are ignored In fact, this helps in the indentation of code to make it easier to read. White space is a term used to represent the characters for spaces, tabs, newlines and formfeeds, and is usually ignored by Verilog except when it separates tokens. Integer a // Creates an int variable called a, and treats everything to the right of // as a comment However, single line comments can be nested in a multiple line comment. A multiple-line comment starts with /* and ends with */ and cannot be nested.A single line comment starts with // and tells Verilog compiler to treat everything after this point to the end of the line as a comment.There are two ways to write comments in Verilog. Verilog is case-sensitive, so var_a and var_A are different. All lines should be terminated by a semi-colon. A lexical token may consist of one or more characters and tokens can be comments, keywords, numbers, strings or white space. Lexical conventions in Verilog are similar to C in the sense that it contains a stream of tokens. Introduction What is Verilog? Introduction to Verilog Chip Design Flow Chip Abstraction Layers Data Types Verilog Syntax Verilog Data types Verilog Scalar/Vector Verilog Arrays Building Blocks Verilog Module Verilog Port Verilog Module Instantiations Verilog assign statements Verilog assign examples Verilog Operators Verilog Concatenation Verilog always block Combo Logic with always Sequential Logic with always Verilog initial block Verilog in a nutshell Verilog generate Behavioral modeling Verilog Block Statements Verilog Assignment Types Verilog Blocking/Non-blocking Verilog Control Flow Verilog if-else-if Verilog Conditional Statements Verilog for Loop Verilog case Statement Verilog Functions Verilog Tasks Verilog Parameters Verilog `ifdef `elsif Verilog Delay Control Verilog Inter/Intra Delay Verilog Hierarchical Reference Verilog Coding Style Effect Gate/Switch modeling Gate Level Modeling Gate Level Examples Gate Delays Switch Level Modeling User-Defined Primitives Simulation Verilog Simulation Basics Verilog Testbench Verilog Timescale Verilog Scheduling Regions Verilog Clock Generator System Tasks and Functions Verilog Display tasks Verilog Math Functions Verilog Timeformat Verilog Timescale Scope Verilog File Operations Code Examples Hello World! Flops and Latches JK Flip-Flop D Flip-Flop T Flip-Flop D Latch Counters 4-bit counter Ripple Counter Straight Ring Counter Johnson Counter Mod-N Counter Gray Counter Misc n-bit Shift Register Binary to Gray Converter Priority Encoder 4x1 multiplexer Full adder Single Port RAM Verilog Pattern Detector Verilog Sequence Detector
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